This is a speculative class project and needs to be refined before being deployed at any scale.

Fig. 1 Used pacemaker showing size (cm)
FA info icon.svg Angle down icon.svg Project data
Authors Daniel Freiberg
Kellan Martin
Location Michigan, USA
OKH Manifest Download

A Pacemaker[1] is a surgically implanted battery operated device used to bypass the "cardiac conduction system where a local or a global malfunction is found".[2] Basically, pacemakers help normalize abnormal heart rates in patients with those types of issues.

Since pacemakers are implanted in patients, size is a huge concern that, presently, is much less of a problem because of the shrinking size of the semiconductor devices used in the pacemakers, which provide the internal clock used to regulate the electric pulses that moderate heart rate in patients.

Pacemakers are implanted into patients just below the skin and are located near to the heart. Additionally a wire connects the pacemaker to the heart in order to send electrical impulses to the heart.[3]

Major Pacemaker, Pacemaker Accessories and Pacemaker Software Manufacturers[edit | edit source]

  • Biotronic Medical[4]
  • Medical Devices[5]
  • Boston Scientific[6]
  • Medico[7]
  • Medtronic[8]
  • Micromedical Industries Ltd.[9]
  • Wilson Greatbatch Ltd.[10]

Semiconductors Used in Pacemakers[edit | edit source]

The general type of semiconductor device that is used in a pacemaker is known as a Complimentary Metal Oxide Semiconductor, CMOS[11] for short. They are used in a variety of electronics ranging from computers to cellphones. A CMOS semiconductor type uses both n-type[12] and p-type transistors which provide logic gates[13] that provide an 'on or off' function for the flow of electricity through the semiconductor device. These functions basically control how the semiconductor device works by controlling the different passages of electricity. There are some very important characteristics that CMOS semiconductors exhibit, which are high noise immunity and low power consumption.[11]A high noise immunity is very useful in pacemakers, as it would be very detrimental for the device and the patient to be severely affected by every type of electromagnetic noise available. Possible pacemaker responses to electromagnetic noise interference are shown as follows:[14]

  • Single Beat Inhibition - Where the pacemaker may not pace the heart for a single cardiac cycle
  • Total Beat Inhibition - Where the pacemaker ceases to pace the heart
  • Noise Reversion/Asynchronous Pacing - Where the pacemaker works at a fixed rate
  • Rate Increase - The pacemaker works at an increased rate
  • Erratic Pacing Rate - Pacemaker function is essentially null

The types of noise interference that can cause these pacemaker responses is as follows:

  • Electrically Coupled Noise - The most common type of noise, usually seen around electronic devices
  • Magnetic Noise - Occurs when a patient gets close to an intense magnetic field
  • Galvanic Noise - Occurs when patient come in direct contact with an electrical current
  • Ultrasonic and Subsonic Noise - Usually only is found in hospitals
  • Ionizing Radiation - Again only found in hospitals with very radiative equipment

As for having a low static power consumption; this is also very key for pacemakers as they are battery powered and a low power consumption will increase the life of the battery.

How is a CMOS Chip Made?[edit | edit source]

The first step in fabrication for a CMOS chip involves the production of a 'nine-nine' (99.9999999% Crystallinity) crystal silicon chip. This is done purely in order to have the best electronic properties needed for seamless operation. This is enacting what is called Single-Crystal Czochralski Growth, which is able to produce a single exceptionally crystalline Silicon ingot by dipping a 'seed' Silicon crystal into molten silicon and then retracting it while rotating the seed holder. While it is withdrawn slowly its cross-sectional area increases and a huge crystalline ingot is produced.

As a result of this process, the final Silicon crystal contains oxygen and other impurities dissolved from the quartz crucible. In order to remove these impurities, a process called Zone Refining is enacted, which melts and then refreezes the Silicon, effectively reducing the impurity concentration in the reheated areas while moving the impurities lengthwise across the ingot. After multiple passes, the impurity concentration on one side of the silicon ingot is basically zero while there are a very concentrated amount of impurities on the opposite side.

Once ultra-high crystallinity of the silicon ingot is obtained the silicon is then sectioned off by use of a diamond saw into what is known as a wafer. This wafer is then ground flat with alumina powder and glycerine, chemically etched, and then polished. For use of CMOS, the wafer is then sectioned off into 'dies' and the silicon die is used as a substrate building block for a number of processes involving implanting and deposition of different elements to make up many layers. A detailed look at how many processes are needed and what they involve for CMOS chip construction are shown in the Table 1.

Table 1. Steps in manufacturing a CMOS transistor[15]

Manufacturing Step process
1 Silicon oxidation on Silicon substrate
2 Boron Implant
3 Boron diffusion to establish p-well
4 Silicon Nitride and Masking
5 Field Boron Implant
6 Field Phosphorus Implant
7 Field Oxide
8 Boron light implant
9 First poly-Si deposition and capacitance plate
10 Arsenic Implant
11 Boron Implant
12 Second poly-Si deposition capacitance plate
13 Aluminum/Copper deposition (metal line network)

Current Scale of the Market[edit | edit source]

Medical devices are becoming smaller and using less power as a result of current advances in semiconductor technology. The total revenue of the medical device semiconductor market is expected to grow from $6 billion to $10 billion by 2016.[16]

Currently North America has the largest market share for pacemakers at 40% where Europe has a 30% share.[17] As of now, annual pacemaker implants for North American and Europe are about 400,000 and 290,000, respectively.[18][19] Asia Pacific makes up for the rest of the global market share and is rapidly growing at an annual compounded rate of 13.3%.[17]The current average cost for a pacemaker in the US ranges from $4,937 to $10,818 as stated by the Berkeley Center for Health Technology.[20] The global market is expected to reach $5.1 billion during the period of 2012 to 2018 with an annual compounded growth rate of 11%.[17]The increase in market share is driven by an increasing elderly population diagnosis of cardiac disorders.

Market Report

Current Recycling Practices for Pacemakers[edit | edit source]

Pacemakers have used a number of different power sources since they were first introduced to the medical world. A particular power source of importance is the radioactive plutonium-238. Disposal of these pacemakers requires contact to the Off-Site Source Recovery Project (OSRP) for direction.[21] In general, used pacemakers are taken from patient bodies and returned to the manufacturer for disposal and/or recycling.[22] Recently there has been a movement to re-purpose used pacemakers for patients who cannot afford the cost of a new pacemaker.[23] Used pacemakers can sell for as little as $400.

Amount of semiconductor in entire market for pacemakers[edit | edit source]

The dimensions of the Medtronic Adapta™ can be found at These dimensions are assumed to be similar for other pacemakers. The CMOS chip is assumed to be 7000 μm by 7000 μm.[24] Additionally, the chip substrate is assumed to be made of silicon wafer with a thickness of 50 μm.[25] The total volume of semiconductor material V can be found using equation 1:

eq (1)

where and are the dimensions of the silicon substrate. The mass of silicon () per CMOS chip can then be found using equation 2:

eq (2)

where is the density of Si and is the volume of the silicon substrate. The total amount semiconductor (,) used in the entire market for pacemakers can be determined using equation 3:

eq (3)

where T is the total amount of pacemakers in the market and m is the mass of semiconductor per pacemaker device. The calculations determining total amount of semiconductor used in pacemakers globally are illustrated in table 2. The total amount of semiconductor (silicon wafer) used annually in pacemaker production is approximately 4.00 kg (Table 2).

Table 2. Total amount of semiconductor material used in pacemaker market annually

length, l (cm) width, w (cm) Height, h (cm) Volume, (cm3) Si density, (g/cm3) mass of semiconductor/device, (kg) pacemakers in global market, T total semiconductor mass in market, A (kg)
0.7 0.7 0.005 2.45E-3 2.33 5.71E-6 690,000 ~4.00

Methods to collect and recycle semiconductor in pacemakers[edit | edit source]

While we did not find any direct ways to recycle semiconductors in pacemakers, we did find ways that Silicon could be collected and re-used in the fabrication process of the CMOS chip, and also re-using parts of the CMOS chip from de-lamination. The following is a list of what we have found to be some recycling methods for a CMOS semiconductor:

  • Collecting Silicon from the sectioning process of the wafer to make dies

During the process of making the 'dies' of Silicon off the wafer, the material left over after cutting can and should be used to be used for recycling.

  • Hydrogen Ion Delamination[26]

Hydrogen ion delamination is a sort of sputtering process that removes layers of material on top of the Silicon die up to a point in which the exposed sub-layers can be used as material to make other semiconductor products.

Choice A or B[edit | edit source]

Table 1 outlines the typical manufacturing process for a CMOS chip, there are many steps, which lead to an inherently complex chip. In order to recycle the chip it must be entirely stripped down to its individual constituents, which would be very difficult. With that said, as a team we have chosen to pursue "choice B" because the amount of semiconductor in pacemakers globally (~4.00 kg) does not lead to a viable means of collecting and recycling pacemaker semiconductor.

We plan to improve the waste recycling of spent silicon after individual chips are stamped from the silicon wafer. That is, we want to improve on the collection method of spent silicon, with the hopes of finding a means to recycle spent silicon into additional wafers.

Viable Collection Methods of Waste Semiconductor Material[edit | edit source]

We decided that we must take steps to collect the waste silicon that is produced during the manufacturing process. Below are the methods that we found that would We have only found one method of collection that would give us the highest purity silicon that would not have to be refined or have multiple steps to extract it. We have also only found one method that would collect silicon post manufacturing, but this would produce silicon that is not high in purity. The two methods we have found are located below:

  • Collecting waste silicon from the crystalline silicon wafer during the process of 'dicing' the 'streets' - This would provide the highest purity silicon even though it is still doped from the dopants added during the Czochralski Process.
  • Using hydrogen ion de-lamination to get to poly-silicon layers and extracting said layers - This method would provide low purity silicon that we could possibly re-melt

Utilization rate of semiconductor[edit | edit source]

Fig. 5 Schematic of silicon wafer disc with semiconductor devices

Figure 5 is a schematic of a silicon wafer with many copies of deposited semiconductor devices. Wafer diameter typically ranges from 100 to 300 mm. The semiconductor devices, which in this case are CMOS chips must be separated from one another. A diamond saw is used to dice (cut) the semiconductor devices along the separating streets, which are depicted as red arrows in Figure 5. As a result of dicing, the saw blade removes a thin section of silicon wafer known as kurf. This kurf will be collected and recycled along with the undeveloped portions of the silicon wafers (red regions in Fig. 5).

It becomes necessary to quantify how much of the silicon wafer is wasted in the manufacturing process. This will first be done by determining the portion of unused or undeveloped region of the silicon wafer. Second the amount of material lost in the cutting process will be determined.

Quantification of Kerf loss per Silicon Wafer[edit | edit source]

A silicon wafer that is completely filled with semiconductor devices will be used for kerf quantification (modify dicin the streets.jpg). Devices are assumed to be 7 mm by 7 mm CMOS chips arranged in a rectangular array on a 200 mm diameter 1 mm thick silicon wafer. Kerf width from the saw blade is assumed to be 0.05 mm and equal to street width.

Calculation of theoretical amount of CMOS chips on wafer[edit | edit source]

NOTE: Theoretical amount of chips will be greater than actual amount of produced chips.

The surface area of the wafer can be calculated using equation 4:

eq. (4) Awafer

where Awafer is the surface area of the wafer in mm2 and D is the diameter of the wafer in mm.

The area of a CMOS chip, Achip is 49 mm2. The total amount of chips not considering street spacing,Cw/o street that can be placed on a wafer is calculated with equation 5:

eq. (5) Cw/o kerfAwafer Achip

When considering the street width the chip length and width are both increased by 0.05 mm giving a new chip area, Achip+kerf of 49.70 mm2.

The total amount of chips that can fit on a wafer when considering street spacing, Cw/ street can be determined using equation 6:

Calculation of kerf[edit | edit source]

eq. (6) Cw/ streetAwafer Achip+kerf

Thus the total kerf volume, Vkerf can be determined using equation 7:

eq. (7) Vkerf(AwaferCw/streetAchip)twafer

Finally an estimate of mass (kg) of kerf loss per silicon wafer due to dicing can be determined using equation 8:

eq. (8) mkerf loss=VkerfpSi

where pSi is the density of Si in g/cm3.

Table 3. Kerf loss due to dicing calculation results

Awafer (mm2) Cw/o kerf (chip/wafer) Cw/ street (chip/wafer) Vkerf (cm3) (g/cm3) mkerfloss(kg)
3.14E4 641 632 4.32E-1 2.33 1.0E-3

The kerf loss due to dicing of wafers can be estimated to be about 1 g or 1 % of the total weight of the wafer. Sony announced in June of this year (2012) that they will raise production of CMOS chips to 60,000 wafers per month.[27] Meaning that kerf loss per month due to dicing will approximately be,

  1. 0E-3 kg/wafer * 60000 wafers/month = 6.0E1 kg or 7.2E2 kg / year

Contaminants[edit | edit source]

Since the diamond saw used to cut the kerfs needs lubricant, there will be some contamination aspect from the lubricant. Ideally, the lubricant that is used cannot have any chance of reacting with the silicon or else contamination to the degree of the silicon losing its electronics grade purity will occur.

Because of this, it would be really dangerous to use any synthetic lubricants, even though it may cool better than a natural lubricant. We have decided that the lubricant of choice would be very pure de-ionized water, though this does not come without the chance of contamination. A report on this specific subject connotes that, since silicon wafers for use in electronics are usually pre-treated with HF to etch. The reaction that takes place between DI water and Silicon is presented below:

Si + 3H2O ----> H2SiO3 + 4 H+ + 4e-

This reaction takes place because the protective, non-reactive, SiO2 layer is removed because of the Hydrofluoric acid etching. Because of the removal of the Oxide layer, water is able to react with the etched silicon and degrade the gate oxide integrity of it.[28] Also expressed in the report is the observation that limiting the time that the etched silicon is in contact with water, and also controlling the pH of the water can reduce the reaction time greatly.

In order to reduce the amount of time that the silicon is in contact with water, it may be useful to put the slurry of silicon in a low temperature oven to accelerate the evaporation process. This method is not fool proof, though, as the silicon may oxidize in an increased temperature environment. The temperature range that silicon is usually oxidized at using a High Temperature Oxidation [HTO] method[29] is from 800 - 1200 degrees Celsius, and so the oven will be put at a temperature way lower than this range, probably at less than 100 degrees Celsius. Since the oxidation rate at HTO temperatures is very small, on average taking about 40 hours for a <100> Si sample to have a 1 micro-meter oxide thickness using dry oxidation methods,[30] we can assume that the oxidation rate at these temperatures will be incredibly lower. This makes us able to say that we would probably get a 98-99% salvation of silicon from the slurry if it is spread out evenly across the heating surface.

Another aspect of contamination for a CMOS semiconductor will be hydrogen ion implantation in the poly-silicon layers of the CMOS chip after the process of hydrogen ion de-lamination. Since this process is pretty violent in the sense that there are hydrogen ions being sputtered at the chip in order to remove the lamination layers, we would not be able to control the chance of hydrogen ions being implanted into the poly-silicon layers. Since Hydrogen is stable as a gas at normal room temperatures, assumptions can be made that if we also perform steps of melting the poly-silicon in a vat to its melting point then we should be able to perform a purification process in the same sense as what is being outlined below in the purification steps of removing dopants from Silicon.

Purification Methods[edit | edit source]

The silicon that would be produced from the wafer saw while 'dicing' the 'streets' in the silicon wafer would already be electronics grade silicon if it is collected in a container that is contaminant free and contains nothing that would add impurities to the silicon that is collected. The only impurities associated with this type of silicon would be the dopants that have been added to the silicon during the ingot formation phase. Because of this, we have theorized that it would be possible to add the silicon collected that has been cut from the wafers back into a vat of already prepared silicon before the process of single crystal Czochralski growth and heat up the vat to the boiling point of whatever dopant is in the vat to essentially purify the silicon by boiling out the impurities.

This method has some viability, as the silicon boiling point is 3538 Kelvin, while the common dopants for electronic silicon and their boiling points are located below:

  • Antimony - 1860 Kelvin
  • Phosphorous - 453.5 Kelvin
  • Arsenic - 875.8 Kelvin
  • Boron - 4200 Kelvin
  • Aluminum - 2792 Kelvin
  • Gallium - 2477 Kelvin

As can be seen, the only element that has a boiling point above that of Silicon is Boron, so there needs to be a different method of purification for Silicon chips that are doped with that element. Luckily, a study has been found that states there is a purification process of these types of Silicon doped chips that has a better result than hydrofluoric acid leaching.[31] This involves alloying Silicon with Aluminum which, when also combined with HF leaching produced a removal ratio of 89.21%.[32]

Quantification of Energy Used[edit | edit source]

In order to heat these elements up to their boiling point for purification there is obviously a need for high amounts of energy to be used for long periods of time. This section will lay out the quantification of the energy usage for all of the dopants listed above except for Boron.

Researching all of the thermodynamic information that is needed, it can be found that the molar heat capacity for crystalline silicon is 19.789 J/Mol*K,[33] and the heat capacity for liquid Silicon was found to be 29.0 J/Gram*K.[34] Converting grams to moles it is found hat the molar heat capacity for liquid silicon is a whopping 813.95 J/Mol*K. In order to do this quantification, the Heat of Fusion for Silicon was needed, which has been measured to be 50.21 kJ/Mol.[33]With all of this information, it is now possible to to quantify how much energy is needed for a melting process.

The melting point of silicon has been found to be 1687 K. Since the molar heat capacity for crystalline silicon is 19.789 J/Mol*K, and assuming only one mole of Silicon is being used for this melting process it can be shown that the amount of heat required to heat crystalline up to this point is, starting at standard temperature:

Si_Melt = 1,414 K * 19.789 J/Mol*K * 1 Mol = 27.981 kJ

Once the silicon gets to its melting temperature with 27.981 kJ it is still not a liquid because enough energy has not been pumped into the system for the Silicon to go from a solid to a liquid. This requires the amount of energy given by the Heat of Fusion, which is 50.71 kJ/Mol. Since we are only using one mole of silicon, the amount of energy needed to get this silicon from a solid to a liquid is:

Si_Liquid = Si_Melt + HoF = 27.981 kJ + 50.71 kJ = 78.69 kJ

After the silicon is melted, the only thing required for purificaton is to heat the liquid Silicon up to the boiling points of all the other elements.[verification needed] Below is a listing of how much energy is needed to heat the molten Silicon up to the boiling points of the doping elements, how much power is required to heat it up to that temperature for one hour, and also the costs of these energy usages based on the average costs of a kiloWatt-Hour obtained.[35] With these calculations it is worth noting that the molar heat capacity for liquid Silicon is.814 kJ/Mol*K, and that there will be an assumption of only 1 mol of substance. This process will only provide a rough estimate of what the energies and work should actually be because of the fact that adding dopants to silicon changes the heat capacity. It should also be noted that these calculations are based on the fact that an equal amount of energy is leaving the systems as is being put in:

The average price of a kWh in the United States is $.21[verification needed]

  • Antimony - Boiling Point: 1,860 Kelvin

E_Antimony =.814 kJ/Mol*K * (1,860K-1,687K) * 1 Mol = 140.82 kJ

W_Antimony = (140,820 Joules + 78,690 Joules)/second = 219,510 Watts or 219.51 Kilo-Watts

The energy required to stay at this temperature for one hour would be - 219,510 Watts * 3,600 Seconds = 790,236,000 Joules or 790.24 Mega-Joules

The cost for having this system get to 1,860 Kelvin for one hour will be C_Antimony = $.21/kWh * 219.51 kW * 1 Hour = $ 46.09

  • Phosphorous - Boiling Point: 453.5 Kelvin

E_Phosphorous = 78.69 kJ

W_Phosphorous = 78690 Joules/second = 78,690 Watts or 78.69 Kilo-Watts

The energy required to stay at this temperature for one hour would be - 78690 Watts * 3600 Seconds = 283,284,000 Joules or 283.28 Mega-Joules

The cost of having this system get to 453.5 Kelvin for one hour will be C_Phosphorous = $.21/kWh * 78.69 kW * 1 Hour = $ 16.52

  • Arsenic - Boiling Point: 875.8 Kelvin

E_Arsenic = 78.69 kJ

W_Arsenic= 78,690 Joules/second = 78,690 Watts or 78.69 Kilo-Watts

The energy required to stay at this temperature for one hour would be - 78,690 Watts * 3,600 Seconds = 283,284,000 Joules or 283.28 Mega-Joules

The cost of having this system get to 875.8 Kelvin for one hour will be C_Arsenic = $.21/kWh * 78.69 kW * 1 Hour = $ 16.52

  • Aluminum - Boiling Point: 2,792 Kelvin

E_Aluminum =.814 kJ/Mol*K * (2,792K - 1,687K) * 1 Mol = 899.47 kJ

W_Aluminum = (899,470 Joules + 78,690 Joules)/second = 978,160 Watts or 978.16 Kilo-Watts

The energy required to stay at this temperature for one hour would be 978,160 Watts * 3,600 Seconds = 3,521,376,000 Joules or 3.52 Giga-Joules

The cost of having this system get to 2,792 Kelvin for one hour will be C_Aluminum = $.21/kWh * 978.16 kW * 1 Hour = $ 205.41

  • Gallium - Boiling Point: 2,477 Kelvin

E_Gallium =.814 kJ/Mol*K * (2,477K - 1,687K) * 1 Mol = 643.06 kJ

W_Gallium = (643,060 Joules + 78,690 Joules)/second = 721,750 Watts or 721.75 Kilo-Watts

The energy required to stay at this temperature for one hour would be 721,750 Watts * 3,600 Seconds = 2,598,300,000 Joules or 2.60 Giga-Joules

The cost of having this system get to 2,477 Kelvin for one hour will be C_Gallium = $.21/kWh * 721.75 kW * 1 Hour = $ 151.57

Down-cycling[edit | edit source]

Down-cycling is defined as "the process of converting waste materials or useless materials into new materials or products of lesser quality or functionality".[36] While down-cycling may not be applicable for the dopant purification process listed above (since we want to make that silicon as pure as possible for electronics), the products of hydrogen ion de-lamination are perfect for down-cycling. This is because it is connoted that CMOS semiconductors stripped down to some part of their constituents can potentially be used as parts of other semiconductors.[26]This stripped down semiconductor can possibly be used for applications where purity of silicon is not a huge factor, so applications in the photovoltaics and monitor display industry could possibly use this down-cycled semiconductor material.

Recycling Plant Layout[edit | edit source]

To carry out the two proposed recycling methods an addition will be made to a currently operational silicon manufacturing facility by installing two recycling process lines. The following shows the general orientation of the processing lines with necessary equipment.


The incoming kerf slurry from a CMOS manufacturing plant will be strained to separate the silicon kerf from the cutting fluid (DI water). The silicon will then be evenly dried by passing through an oven. The dried silicon will then be dumped into a purification vat. The purified silicon can then be used for silicon ingot production.

Hydrogen ion de-lamination will have a dedicated process line that will strictly process defective chips from a given CMOS manufacturing facility. Incoming defective chips will be collected in a large bin. The chips will then pass into an orientation machine, which ensures the chips are right side up for subsequent continuous hydrogen ion de-lamination. After de-lamination, the purified chips will then be used for silicon ingot manufacture.

MSDS Sheets for Chemicals Used[edit | edit source]

Material Flowchart[edit | edit source]


References[edit | edit source]

  1. National Heart Lung and Blood Institute Pacemaker Information
  2. VLSI for Pacemaker Application
  3. Boston Scientific Life Beat
  4. Biotronic Medical
  5. CCC Medical Devices
  6. Boston Scientific
  7. Medico
  8. Medtronic
  9. Micromedical Industries Ltd.
  10. Wilson Greatbatch Ltd.
  11. 11.0 11.1 Wikipedia CMOS Information
  12. N-Type and P-Type Transistor Information
  13. Wikipedia Logic Gates Article
  14. Interference: Its Potential Effect on Pacemaker Systems
  15. The CMOS Technology
  16. Overview of the Medical Semiconductor Market and Applications
  17. 17.0 17.1 17.2 Cardiac Pacemakers Market - Global Industry Size, Share, Trends, Analysis, and Forecasts 2012 - 2018
  18. Pacemaker and Defibrillator Lead Extraction
  19. Pacing for bradyarrythmias Survey
  20. [ Pacemaker and Implantable Cardioverter-Defi brillator (ICD) Implant Procedures in California Hospitals]
  21. Los Alamos National Laboratory
  22. [1] Pacemaker System Specification, Boston Scientific
  23. [2] Waste & Recycling News
  24. A Very Low-Power CMOS Mixed-Signal IC for Implantable Pacemaker Applications IEEE Journal
  25. Silicon Valley Microelectronics
  26. 26.0 26.1 Patent on Hydrogen Ion Delamination
  27. Sony raises production to 60,000 wafers per month
  29. Thermal Oxidation Wikipedia Page
  30. Silicon Oxidation Information
  31. Leaching Information
  32. Research on Removal of Boron from Metallurgical Grade Silicon by Si-Al Alloying
  33. 33.0 33.1 Silicon Wikipedia Page
  34. Density and Heat Capacity of Silicon
  35. Average Prices of Energy Consumption
  36. Downcycling Wikipedia Page

FA info icon.svg Angle down icon.svg Page data
Part of MY3701
Keywords recycling, semiconductors, pacemakers
SDG SDG12 Responsible consumption and production
Authors Kellan Martin, Daniel Freiberg
License CC-BY-SA-3.0
Organizations MTU
Language English (en)
Related 0 subpages, 5 pages link here
Impact 1,135 page views
Created September 16, 2012 by Daniel Freiberg
Modified February 28, 2024 by Felipe Schenone
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